1. Field of the Invention
The present invention relates to an assertion description conversion device, a method and a computer program product, and particularly to an assertion description conversion device and a method for converting an assertion description for verification of a design description of a broader term into an assertion description for verification of a design description of a narrower term.
2. Description of the Related Art
The scale of circuits mounted on an LSI has increased accompanying a recent increase in the integration density of LSIs. In response to the increase in the circuit scale, the efficiency of LSI design needs to be enhanced and the level of abstraction of an LSI is on the increase. In other words, broader-term design has been developed in the sense that the design has been progressing from a function-level design on a Resister Transfer Level (RTL) by the conventional description of a Hardware Description Language (HDL) to an operation-level design by the description of a base language of the C language, such as the SystemC. In this operation-level design, broader-term design has also been developed in the sense that the design has been progressing from an low-level I/O cycle operation description of clock synchronization to a high-level transaction level operation description.
In response to the increase of the level of abstraction at a design level, design verification has been made efficient, and various kinds of methods of design verification have been developed. One of such methods is an assertion verification method. In the assertion verification, an assertion description is created in which an assertion corresponds to each design level, that is, a “condition to be,” is described, and whether a design description of each of the level violates the assertion is checked.
In order to create an assertion description corresponds to each design level, for a design description at an operation level, an assertion description is created using the SystemC, for example, and for a design description at a function level, an assertion description is created by the System Verilog Assertion (SVA), for example.
Thus, it is necessary to create one assertion description for a design description of every design level. When such an assertion description is created manually, it requires a lot, and errors tend to be involved. Further, when the design of a broader term is changed after the assertion description for the design description of a narrower term is created, a new assertion description for the design description of the narrower concept needs to be created, and consequently, the creation of assertion descriptions becomes inefficient. To solve these problems, an LSI design verification device has been proposed, which mechanically generates, for example, an assertion description for an RTL description (for example, refer to Japanese Patent Application Laid-open Publication No. 2005-108007 (pp. 10-11, FIG. 1)).
However, in the case of the above-mentioned LSI design verification device, there is a problem that it takes time to generate an assertion description for an RTL description. This is caused because, to create an assertion description for an RTL description, it is necessary to execute an operation simulation for a design description of a broader term at an operation level.